Switch mode power circuit

ABSTRACT

There is provided a switch mode power supply circuit including at least one inductive component coupled to an associated switching device for cyclically connecting the inductive component to a source of power. The circuit includes a signal output representative of a voltage at a junction of the at least one inductive component to the switching device. The circuit further comprises a hard switching amplitude detector for deriving a measure of hard switching amplitude occurring in operation in the switching device the detector including a signal processing path for receiving the signal output and generating the measure of hard switching amplitude therefrom. The signal path includes: a signal differentiator for imperfectly differentiating the signal output to generate a corresponding imperfectly differentiated signal; and a signal integrator for integrating the imperfectly differentiated signal in a temporally-gated manner for generating the measure of hard switching.

FIELD OF THE INVENTION

The present invention relates to switch mode power circuits, for exampleto switch mode motor controllers and to switch mode power supplies; inparticular, but not exclusively, the invention relates to a switch modepower circuit including features for detecting hard switching amplitudetherein. Moreover, the invention also relates to a method of detectinghard switching amplitude of a hard switch moment in switch mode powercircuits, for example a method of detecting hard switching amplitude inswitch mode power supplies.

BACKGROUND TO THE INVENTION

Switching mode power circuits are well known, for example switch modepower supplies and switch mode motor controllers. Such circuits usuallyinclude one or more electronic power switching devices, for example afield effect transistor (FET), a bipolar switching transistor, a triacand/or a silicon controlled rectifier (SCR). Increasingly, on account oftheir relatively faster switching speed enabling coincidental use ofmore compact magnetic components such as ferrite transformers, FETs arebecoming increasingly employed in switch mode power circuits.

An important parameter for consideration when designing switch modepower circuits is hard switching amplitude; hard switching amplitude isdefined as a voltage developed across a switching device at a momentwhereat the device is driven into a conductive state, namely turned on.

U.S. Pat. No. 6,069,804 describes a multi-output, multi-directionalpower converter that has an input bi-directional switch and at least afirst output bi-directional switch. Moreover, the converter furthercomprises a coupled inductor having an input winding and at least oneoutput winding. The input winding is connected in series with an inputvoltage source and an input bi-directional switch implemented using FETtechnology. Each coupled inductor output winding is connected in serieswith a corresponding output voltage source, for example a capacitor, andits respective output bi-direction switch also implemented using FETtechnology. The converter additionally includes a clock circuit forproviding first and second control signals, each signal having first andsecond states. The first and second signals are connected to the inputand output switches respectively. Moreover, the first and second signalsare arranged to be substantially mutually complementary with regard totheir states.

The power converter is susceptible to being modified to include resonanttransition controlling means for sensing currents in the input andoutput windings as well as output voltage and from such current sensingtogether with a measure of output voltage from the converter foradjusting a clocking frequency of the converter for enabling theconverter to function in a resonant mode.

The converter is potentially expensive to implement on account of itsclock circuit being coupled to both input and output sides of thecoupled inductor, such connection requiring additional couplingtransformers to be included for controlling the switches. Moreover, theconverter does not utilize hard switching amplitude information as anaspect of its operation.

U.S. Pat. No. 6,433,491 describes a method of generating a signalcorresponding to hard switching amplitude. The method concerns the useof a capacitive divider for sensing primary winding potential in atransformer-coupled device. The method involves temporally controlledresetting of the divider in conjunction with a sample-and-hold circuitfor providing a direct indication of the hard switching magnitude.However, the method requires precise timing information and is directlyassociated with the primary winding which is potentially at relativelyhigh potentials, for example as in mains-supplied SMPS. Thus, this U.S.patent is regarded as elucidating a non-optimal method of determininghard switching amplitude.

The inventor has appreciated that it is desirable, for example not onlyin the aforementioned method but also in the power controller and othersimilar types of switch mode circuits such as switch mode powersupplies, to measure hard switching amplitude. For example, in a switchmode power supply (SMPS) system, switching losses occur if one or morepower controlling switching devices therein are turned on, namely drivento a conductive state, whilst a non-zero potential is developed thereacross.

In some SMPS applications, hard switching is unavoidable and the hardswitching amplitude is variable, for example in response to changingSMPS loading conditions. In such circumstances, it is often desirable toprovide regulation to other components depending upon this amplitude,for example for providing circuit protection shutdown in an event ofcircuit overload. Moreover, timing information pertaining to occurrenceof such hard switching is often not available or relatively expensive toobtain, for example on account of a need to include additional isolationcomponents where mains electrical input supplies are involved. Anexample of such a SMPS application is a bi-directional flyback converterincluding a transformer with primary and secondary windings, the primarywinding being connected to a primary FET switching device; preferably,the primary device is turned on, namely switched to a conducting state,whilst a voltage developed there across is almost of zero magnitude,namely the primary device is preferably subject to soft switching. Therethereby arises a need to monitor the hard switching amplitude of the FETdevice, such monitoring conventionally being achieved by including acontrol loop implemented substantially around circuits associated withthe secondary windings. Thus, the hard switching amplitude isconventionally monitored at a secondary region of the bi-directionalconverter by monitoring a voltage developed across one of itstransformer windings. In such a configuration, precise switching timinginformation pertaining to the primary windings is not normally availableat the secondary circuit unless additional potentially expensivecomponents are included.

The inventor has appreciated that it is especially desirable to be ableto determine hard switching amplitude in switch mode circuits includingtransformer-type components by monitoring a signal developed across asecondary winding of such transformer-type components without therebeing a need to generate precise temporal information, therebypotentially reducing the cost and complexity of such switch modecircuits.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an improved switched modepower supply. The invention is defined by the independent claims. Thedependent claims define advantageous embodiments.

The invention is of advantage in that the circuit is capable of yieldingthe measure of hard switching amplitude in a manner that is at least oneof less expensive, less complex, and more accurate in comparison toconventional approaches to determining such a measure of hard switchingamplitude.

Preferably, the detector further includes timing means for applyingtemporal gating to the integrating means. The timing means is of benefitin that it enables a particular portion of the signal output moresignificantly influenced in response to changes in hard switchingamplitude to be selected for purposes of generating the measure of hardswitching amplitude.

More preferably, the timing means is also arranged to provide temporalgating to the differentiating means. Such additional temporal gating ofthe differentiating means is capable of improving accuracy of thedetector when generating its measure of hard switching amplitude.

Preferably, in order to provide an nearly instantaneous and potentiallymore accurate measure of the hard switching amplitude, the timing meansis arranged to reset at least one of the differentiating means and theintegrating means for each conduction cycle of the switching means. Suchresetting is capable of enabling the circuit to generate the measure ofhard switching amplitude that is substantially instantaneously updated.

Preferably, for example to reduce circuit cost and complexity as well asproviding electrical isolation in a straightforward manner, thedifferentiating means is implemented as a potential divider combinationof a resistor and an associated capacitor, the resistor and capacitordefining an associated time constant capable of rendering thecombination susceptible to providing imperfect differentiation of thesignal output suitable for use in generating the measure of hardswitching amplitude.

Preferably, the circuit is susceptible for use in at least one of:switch mode power supplies, motor controllers, battery chargers,ionizing apparatus, high-tension bias generators. The measure of hardswitching amplitude is susceptible to being used for one or more offeedback regulation, overload protection and power monitoring.

It will be appreciated that features of the invention are susceptible tobeing combined in any combination without departing from the scope ofthe invention.

DESCRIPTION OF THE DIAGRAMS

Embodiments of the invention will now be described, by way of exampleonly, wherein:

FIG. 1 is a schematic diagram of a known switch mode power supply (SMPS)implemented as a bidifly converter;

FIG. 2 is a graph illustrating operation of the supply of FIG. 1;

FIG. 3 is a graph illustrating temporal differentiation followed bytemporal integration for recreating a potential arising in operation ata primary switch of the supply of FIG. 1;

FIG. 4 is a graph illustrating imperfect differentiation followed bytemporally gated integration to derive a measure of hard switchingamplitude, V_(hard);

FIG. 5 is a schematic diagram of a first embodiment of the invention;and

FIG. 6 is a temporal switching diagram pertaining the embodimentillustrated in FIG. 5.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In order to elucidate the present invention, a conventional approach tomeasure hard switching amplitude will firstly be described in detailfollowed by a description of embodiments of the present invention inorder to juxtapose the present invention more clearly with respect tothe prior art.

In FIG. 1, there is shown a schematic diagram of a conventional switchmode power supply (SMPS) implemented as a bi-directional fly-backconverter, known often as a bidifly converter; the supply is indicatedgenerally by 10. The supply 10 comprises a ferrite-cored transformer TRIcomprising a primary winding L_(prim), and first and second secondarywindings L_(sec1), L_(sec2) respectively. The primary winding L_(prim)is electrically isolated from the secondary windings L_(sec1), L_(sec2).Moreover, the primary winding L_(prim) is connected in series with aprimary field effect transistor switch FET SW1 and mains electricalsupply V_(mains). The mains supply V_(mains) is susceptible, forexample, to being provided from an alternating mains supply by way of asuitable high-voltage bridge rectifier coupled to electrolytic storagecapacitors (not shown).

The primary switch FET SW1 includes a parasitic drain-source capacitanceC_(par) as a consequence of its mode of fabrication. A gate electrode ofthe primary switch FET SW1 is coupled to a primary drive circuit 30.

The second secondary winding L_(sec2) is coupled via a rectifier diodeD₁ to a capacitor C₂ across which, in operation, a voltage differenceV_(out2) is generated. Similarly, the first secondary winding isconnected in series with a capacitor C₁ and a secondary field effecttransistor switch FET SW2 as shown; in operation, a voltage differenceV_(out1) is developed across the capacitor C₁. An output junctionwhereat the primary winding L_(prim) is coupled to the primary switchFET SW1 defines a voltage difference Vp_(rim) as illustrated. Likewise,an output junction whereat the first secondary winding L_(sec1) isconnected to the secondary switch FET SW2 defines an output voltageV_(sec) which is coupled to a hard switching amplitude detector (SW DET)20; the switching detector 20 includes, amongst other components, asample-and-hold circuit whose operation is susceptible to beingprecisely time gated. The secondary switch FET SW2 is driven from a Qoutput of a flip-flop 35 whose reset input R is coupled to a circuit(not shown) operable to switch the switch FET SW2 to a non-conductingoff state when a magnetizing current I_(magn) is less than a referencecurrent I_(ref); the current I_(magn) is defined later. Moreover, theflip-flop 35 includes a set input S coupled to a start secondary stroke(ST. SEC. STR.) line for causing the secondary switch FET SW2 to conductin an on state when this line assumes a logic 1 state.

Referring to FIG. 2, there is shown a temporal graph indicated generallyby 40, the graph 40 pertaining to operation of the supply 10. The graph40 comprises an abscissa axis 50 denoting time T. Moreover, the graph 40further comprises a first ordinate axis 60 a denoting magnetizingcurrent I_(magn) corresponding to a summation of currents flowing in allwindings of the transformer TR1 referred to a primary side thereof, suchreferral taking into account turns ration of the primary and secondarywindings L_(prim), L_(sec1), L_(sec2). Furthermore, the graph 40additionally comprises a second ordinate axis 60 b denoting the voltagedifference V_(prim) as indicated in FIG. 1, namely a potential at ajunction where the primary switch PET SW1 is coupled to the primarywinding L_(prim).

Operation of the supply 10 will now be described in overview withreference to FIGS. 1 and 2. During a time period t_(0b) in the graph 40,namely during a latter part of a time period t₀ in which a magnetizingcurrent through the primary winding L_(prim) is increasing, the primaryswitch FET SW1 is in a conducting state causing the voltage V_(prim) tobe substantially close to zero across the switch FET SW1. Themagnetizing current through the primary winding L_(prim) increases fromsubstantially zero magnitude during this period t_(0b) as illustratedrelative to the ordinate axis 60 a. In contradistinction, during a timeperiod t₁ in the graph 40, the summated magnetizing current I_(magn)decreases progressively to finally a value I_(ref) as illustrated.During the period t_(0a), the voltage V_(prim) exhibits a progressivedecay 70 caused by resonant ringing arising on account of there beingcreated a resonant circuit comprising the parasitic capacitance C_(par)of the primary switch FET SW1 and the inductance of the primary windingL_(prim). The progressive decay 70 is followed by a sharp decay denotedby 75 indicative of hard switching occurring in the FET SW1. In FIG. 2,instances F1, F2, F3, F4 correspond to:

-   (a) F1: switch-off of the primary switch FET SW1;-   (b) F2: switch-off of the secondary switch FET SW2;-   (c) F3: switch on of the primary switch FET SW1; and-   (d) F4: switch-on of the secondary switch FET SW2.

During the period t_(0b), current through the primary winding L_(prim)establishes a magnetic field in the transformer TR1, the fieldsubsequently decaying again in its subsequent period t₁. The secondaryswitch FET SW2 is driven by its associated flip-flop to conduct totransfer magnetic energy stored within the transformer TR1 to thecapacitor C₁. The supply 10 exploits a useful characteristic in that anegative value of I_(magn) charges the capacitor C_(par) at the end ofthe period t₁ with a consequence that the primary switch FET SW1 isswitched to a conductive state with a relatively low potential thereacross, thereby reducing switching losses arising in operation in thesupply 10. Preferably, the magnitude of a reference current I_(ref) iscontrolled by a potential V_(hard) indicative of the hard switchingamplitude at switch-on of the primary switch FET SW1. On account of aneed for mains isolation between the primary winding L_(prim) relativeto the windings L_(sec1), L_(sec2), it is conventional practice todetermine the hard switching amplitude V_(hard) at one or more of thesecondary windings L_(sec 1), L_(sec2). However, conventional approachesto determining the hard switching amplitude at the secondary windingshave hitherto been one or more of inconveniently expensive andinsufficiently accurate. The inventor has therefore appreciated that animproved method of measuring hard switching amplitude at secondarywindings L_(sec1), L_(sec2) is potentially of advantage.

In a conventional bidifly-type converter, the inventor has appreciatedthat it is desirable to discriminate between ringing that occurs afterswitch-on of the primary switch FET SW1 from a steep slope, for exampleas represented by 70 in FIG. 2, arising at an instance the primaryswitch FET SW1 is driven to its conducting state, for example asrepresented by 75 in FIG. 2. In order to provide such discrimination, itwould be conventionally anticipated that precise timing signals wouldneed to be provided within the supply 10. As timing signals associatedwith the primary switch FET SW1 are available in the supply 10, thesesignals are beneficially employed for measuring the hard switchingamplitude and have been previously investigated by the inventor in thecontext of televisions and related visual monitor units.

The inventor has appreciated that an original signal can be temporallydifferentiated to provide a corresponded differentiated signal.Moreover, the inventor has also envisaged that the original signal issusceptible to be regenerated by applying integration to thedifferentiated signal. Indeed, the inventor has appreciated that a partof the differentiated signal is also susceptible to be integrated tosubstantially regenerate a corresponding portion of the original signal.For example, in the supply 10, the voltage V_(prim), or a correspondingversion thereof available at one or more of the secondary windingsL_(sec1), L_(sec2), is susceptible to being differentiated to provide acorresponding differentiated signal dV_(prim)/dt, wherein a measure of acurrent flowing through the capacitor C_(par) can thereby be derived.The current flowing through the capacitor C_(par) is substantially equalto the current flowing though the primary winding L_(prim) duringtrailing and leading edges of each conduction cycle, namely stroke, ofthe primary switch FET SW1. Thus, by integrating the differentiatedsignal dV_(prim)/dt using an integrator, it is feasible to recreate ameasure of the voltage V_(prim). In a situation where an idealdifferentiator is employed to generate the signal dV_(prim)/dt, thedifferentiator only generates a useful signal during a time whererelatively rapid change in the voltage V_(prim) occurs in the supply 10.

The inventor has appreciated that, for purposes of controlling operationof the supply 10, it is desirable to measure the voltage over thecapacitor C_(par) especially when the primary switch FET SW1 isswitching on to its conducting state corresponding to the progressivedecay 70 in FIG. 2. The decay 70 is of a temporal duration includingdischarging of the capacitor C_(par). In practice, this temporalduration is in the order of 10 ns. Generating precise timing signals forsuch relatively short durations is potentially a problem.

Referring to FIG. 3, there is shown a graph indicated generally by 100in which the voltage V_(prim) developed at the primary winding L_(prim)is shown against the ordinate axis 60 b in a similar manner to FIG. 2.Moreover, against an ordinate axis 110 a, there is shown a temporallydifferential version of the voltage V_(prim), namely a signaldV_(prim)/dt. It will be appreciated from FIG. 3 that the signaldV_(prim)/dt is susceptible to being integrated to recreate the signalV_(prim) as illustrated against an ordinate axis 110 b.

The inventor has appreciated that an area under differential peaks 150corresponding to switch-on of the primary switch FET SW1 is of interest.Moreover, for hard switching amplitude control purposes, the inventorhas also identified that it is desirable to regenerate the voltageV_(prim) from an instance in each cycle whereat hard switchingcommences. Thus, if a non-ideal differentiator were employed, an areaunder the peaks 150 becomes effectively distributed over a relativelylonger time period. An output from such a non-ideal differentiator issusceptible to being integrated wherein a leading hard switching peak150 can be used as a timing signal for commencing integration.Preferably, a time constant for the differentiator is chosen to berelatively large and integration is beneficially completed before asubsequent conduction cycle, namely stroke, of the primary switch FETSW1 occurs. More preferably, the differentiator is implemented using anetwork comprising a resistor R_(d) connected to an associated capacitorC_(d) whose time constant τ=R_(d) C_(d) is 25% or less of the timeinterval t₀ shown in FIG. 2. Optionally, the signal V_(prim) provided tothe differentiator is susceptible to being suppressed for a periodlonger then the time t₀ to allow for longer integration times to beemployed.

Thus, there arise first and second methods M1, M2 for deriving anindication of hard switching amplitude in the supply 10 using animperfect differentiator coupled in series with a temporally-gatedintegrator for processing an input signal corresponding to the voltageV_(prim). These two methods are schematically illustrated in FIG. 4wherein is included a graph indicated by 200.

In the first method M1, the voltage V_(prim) arising at the primaryswitch FET SW1 is coupled through an imperfect R_(d) C_(d)differentiator as described in the foregoing to an integrator which istemporally gated for a period τ₁ as illustrated, wherein the presence ofa first peak 210 is used for timing control/synchronization for theperiod τ₁. An output of the integrator at the end of the period τ₁ isthen indicative of hard switching amplitude V_(hard) arising in theprimary switch PET SW1. In the first method M1, it is necessary tocommence integration without earlier history of the differentiatoroutput; preferably therefore, immediately prior to the period τ₁, theresistance R_(d) of the differentiator is preferably shorted across itsterminals, for example by using an analog FET switch as will bedescribed in more detail later, for resetting purposes.

In the second method M2, the voltage V_(prim) arising at the primaryswitch FET SW1 is coupled through the imperfect R_(d) C_(d)differentiator to the aforementioned integrator, which is temporallygated for a period τ₂ as illustrated. The period τ₂ encompasses aswitch-off transition of the primary switch FET SW1 but is disabled withregard to its subsequent hard switch-on transition and additional timethere around rendering integrator gate timing for the second method lesscritical; preferably the period τ₂ includes a complete conduction cycleexcluding an initial hard switching period. An output of the integratorat the end of the period τ₂ is indicative of hard switching amplitude,V_(hard).

In order to further elucidate the invention, an embodiment thereof willnow be described with reference to FIG. 5. In FIG. 5, there is shown thesupply including its transformer TR1 with its first secondary windingL_(sec1) together with the aforementioned capacitor C₁, its secondaryswitch FET SW2 coupled to its corresponding flip-flop 35. The supply inFIG. 5 is also providing with a hard switching amplitude detectorindicated generally by 300 and included within a dashed line 305. Thedetector 300 comprises an imperfect differentiator 310, atemporally-gate integrator 320 and a control unit 330 for providingtemporal gating signals DISDIF, DISINT to the differentiator 310 and tothe integrator 320 respectively. An output signal line V_(hard) from theintegrator 320 is arranged to provide a measure of hard switchingamplitude arising in the primary switch FET SW1 during operation. Thesignals DISDIF, DISINT are arranged to be capable of resetting thedifferentiator 310 and the integrator 320 respectively. Moreover, thecontrol unit 330 is provided with an input signal line HSE for receivinga signal generally indicative of a time interval in which hard switch isexpected but not temporally exact in contradistinction to the prior art.

The differentiator 310 comprises a capacitor C_(d) including first andsecond terminals. The first terminal is to the junction of the secondaryswitch FET SW2 and the first secondary winding L_(sec1) as illustrated.The second terminal of the capacitor C_(d) is coupled to a firstterminal of a resistor R_(d) and to a first switch terminal of a FETswitch FET SW3. A second terminal of the resistor R_(d) and a secondswitch terminal of the switch FET SW3 are both coupled to a signalground. At the second terminal of the capacitor C_(d), there is providedan imperfect differential signal output designated DVDT. A control inputof the switch FET SW3 is connected to a signal line DISDIF for disablingthe differentiator 310. Temporal switching of the differentiator 310will be described in more detail later. The differentiator 310 isoperable to provide a transfer function describable in Laplacian form ofEquation 1 (Eq. 1):

$\begin{matrix}{{DVDT} = {\left\lbrack \frac{{sR}_{d}C_{d}}{\left( {1 + {{sR}_{d}C_{d}}} \right)} \right\rbrack V_{\sec}}} & {{Eq}.\mspace{14mu} 1}\end{matrix}$where s if the Laplacian operator.

The integrator 320 includes a current source 325 whose output current iis linearly related to the signal DVDT by a proportionality constant k₁.An output of the source 325 is connected to a first terminal of anintegration capacitor C_(int) and to a first switch terminal of a FETswitch FET SW4. A second terminal of the capacitor C_(int) and a secondswitch terminal of the switch FET SW4 is coupled to the aforesaid signalground.

A signal generated in operation at the first terminal of the capacitorC_(int) is the signal V_(hard) indicative of hard switching amplitudearising in the first primary switch FET SW1 described earlier. Moreover,the integrator 320 is operable to provide a Laplacian transfer functionas defined in Equation 2 (Eq. 2):

$\begin{matrix}{V_{hard} = {\left\lbrack {\left( \frac{1}{{sC}_{int}} \right)k_{1}{DVDT}} \right\rbrack + k_{0}}} & {{Eq}.\mspace{14mu} 2}\end{matrix}$where k₁, k₀ are operating constants of the integrator 320.

Combining Equations 1 and 2 yields an overall Laplacian transferfunction as provided in Equation 3 (Eq. 3):

$\begin{matrix}{V_{hard} = {\left\lbrack {\left( \frac{1}{{sC}_{int}} \right){k_{1}\left\lbrack \frac{{sR}_{d}C_{d}}{\left( {1 + {{sR}_{d}C_{d}}} \right)} \right\rbrack}V_{\sec}} \right\rbrack + k_{0}}} & {{{Eq}.\mspace{14mu} 3}\;}\end{matrix}$

By appropriate temporal switching which will be described later,significance of the terms sR_(d)C_(d) relative to unity (1) in thedenominator of Equations 1 and 3 are susceptible to being used to derivea measure of the hard switching amplitude of the primary switch FET SW1.

The control unit 330 includes an input capacitor C_(c) which isconnected at its first terminal to the V_(sec) signal output of thefirst secondary winding L_(sec1), and at its second terminal to a firstterminal of a resistor R_(c), to a first switch terminal of an analogswitch FET SW5 and to the V_(hard) output indicative in operation ofhard switching amplitude. Moreover, a second terminal of the resistorR_(c) and a second switch terminal of the switch FET SW5 are coupled tothe aforesaid signal ground, as illustrated. Furthermore, the HSE inputis coupled via a logic inverter 340 to a switching control input of theswitch FET SW5 as shown. A signal developed at the first terminal of theresistor R_(c) is coupled into a comparator 350 configured, withadditional components if required (not shown), to exhibit a hysteresischaracteristic to generate the aforementioned signals DISDIF and DISINT.

In FIG. 5, it will be appreciated that the hard switching amplitudedetector 300 is shown coupled to the SMPS 10 but is also suitable forconnected to other types of electronic switching circuits, for exampleswitch mode motor control circuits suitable for applying power toswitched-reluctance motors, traction assemblies such as conveyor belts,battery chargers, fluorescent lighting devices, high voltage ionizers,ionizing water purifiers and linear actuators to mention just a fewexamples.

In order to describe operation of the detector 300, FIG. 6 will also bereferred to in conjunction with FIG. 5. In the first method implementedin the detector 300 of FIG. 5, a downward conducting stroke of theprimary switch FET SW1 generates the aforementioned peaks 150 asillustrated. The HSE signal is arranged to remain in an on state for aperiod including the peaks 150 and time there around. The differentiator310 is disabled by way of its switch FET SW3 shorting the resistor R_(d)in response to the DISDIF signal from the control unit 330 for a periodincluding the peak 210 but excluding its subsequent peak 215. Likewise,the integrator 320 is similarly disabled by way of its switch FET SW4shorting the capacitor C_(int) in response to the signal DISINT asillustrated, such disablement including a period of the primary upwardstroke of the primary switch FET SW1. As a consequence, the peak 210 issusceptible to providing precise timing information, whereas the peak215 includes information relevant for deriving a measure of the hardswitching amplitude V_(hard). For each switching cycle of the primaryswitch FET SW1, the detector 300 is capable of measuring the hardswitching amplitude V_(hard) and providing a corresponding output fromthe detector 300.

Thus, the control unit 330 is operable to sense the signal V_(sec) andgenerate the DISINT, DISDIV signals therefrom by way of action of thehysteresis comparator 350. The HSE signal is operable to disable asecond differentiator formed by the resistor R_(d) and its associatedcapacitor C_(c), thereby preventing the DVDT signal provided to theintegrator 320 from disturbance outside a time window wherein hardswitching is expected. However, inclusion of the DISIT signal is notessential for the invention. At a moment that a hard switch moment isdetected, the DISINT signals is set to a logic OFF state and integrationof an effective area under the DVDT signal starts.

The detector 300 is also susceptible to being operated in theaforementioned second method M2, wherein resetting of the differentiator310 is required. As illustrated in FIG. 4, the integrator 320 isswitched by way of the control unit 330 coupled by the output DISINT tothe switch FET SW4. In the second method M2, integration of the outputof the differentiator 310 occurs through the period τ₂ encompassingupward strokes and corresponding subsequent downward strokes of the ofthe primary switch FET SW1 as illustrated but excluding contributionfrom any hard-switching transient.

Finally, the BIDIFLY signal indicates when the switch SW2 is ON and OFF.

It will be appreciated that embodiments of the invention described inthe foregoing are susceptible to modification without departing from thescope of the invention. For example, although the generation of animperfect integrator and/or an imperfect differentiator using one ormore capacitive components connected in combination with one or moreresistive components is described, it will be appreciated that one ofmore resistive components connected in combination with one or moreinductive components may be employed as an alternative configuration forachieving imperfect integration and/or differentiation.

The detector 300, either implemented using analog components in ananalog manner or in a digital manner using one or more of digitalcomponents and software, or a mixture of these manners, is capable ofbeing applied to a wide range of switch mode circuits for deriving ameasure of hard switching amplitude occurring therein. This amplitudecan be employed to control potentially several different functions suchas overload shutdown, regulation, and switching in of other circuits andsubsystems.

In the foregoing, it will be appreciated that the singular is alsointended to include the plural. Similarly, expressions such as“include”, “contain”, “comprise”, “have” are intended to be construed asnon-exclusive, namely to allow for the presence of other items.

In the claims, any reference signs placed between parentheses shall notbe construed as limiting the claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.In the device claim enumerating several means, several of these meansmay be embodied by one and the same item of hardware. The mere fact thatcertain measures are recited in mutually different dependent claims doesnot indicate that a combination of these measures cannot be used toadvantage.

1. A switch mode power supply circuit including at least one inductivecomponent coupled to an associated switch for cyclically connecting theinductive component to a source of power, the circuit including a signaloutput representative of a voltage at a junction of the at least oneinductive component to the associated switch, the circuit furthercomprising a hard switching amplitude detector for deriving a measure ofhard switching amplitude occurring in operation in the associatedswitch, the detector including a signal processing path for receivingthe signal output and generating the measure of hard switching amplitudetherefrom, the signal path including: a signal differentiator circuitfor imperfectly differentiating the signal output to generate acorresponding imperfectly differentiated signal; and a signal integratorcircuit for integrating the imperfectly differentiated signal in atemporally-gated manner for generating the measure of hard switching. 2.A circuit according to claim 1, wherein the detector further includes atiming circuit for applying temporal gating to the integrator circuit.3. A circuit according to claim 2, wherein the timing circuit isarranged to provide temporal gating to the differentiator circuit.
 4. Acircuit according to claim 2, wherein the timing circuit is arranged toreset at least one of the differentiator circuit and the integratorcircuit for each conduction cycle of the associated switch.
 5. A circuitaccording to claim 1, wherein each conduction cycle of the associatedswitch has associated therewith, in operation: a downward stroke whereatthe associated switch switches from a non-conductive state to aconductive state; and an upward stroke whereat the associated switchswitches from a conductive state to a non-conductive state, the detectorbeing arranged so as to be capable of imperfectly differentiating andsubsequently integrating the output signal in a period commencingshortly prior to the upward stroke and ending shortly after completionof the downward stroke of each cycle for deriving the measure of hardswitching amplitude during that cycle.
 6. A circuit according to claim1, wherein each conduction cycle of the associated switch has associatedtherewith, in operation: a downward stroke whereat the associated switchswitches from a non-conductive state to a conductive state; and anupward stroke whereat the associated switch switches from a conductivestate to a non-conductive state, the detector being arranged so as to becapable of imperfectly differentiating and subsequently integrating theoutput signal in a period; commencing from the end of a firstdifferential signal peak arising from the downward stroke of each cycleto include a subsequent second differential signal peak arising withinthe cycle after the first peaks; and ending within or after the seconddifferential signal peak, for deriving the measure of hard switchingamplitude during that cycle.
 7. A circuit according to claim 1, whereinthe differentiator circuit is implemented as a potential dividercombination of a resistor and an associated capacitor, the resistor andcapacitor defining an associated time constant capable of rendering thecombination susceptible to providing imperfect differentiation of thesignal output suitable for use in generating the measure of hardswitching amplitude.
 8. A circuit according to claim 1, wherein thedifferentiator circuit is implemented as a potential divider combinationof a resistor and an associated inductor, the resistor and inductordefining an associated time constant capable of rendering thecombination susceptible to providing imperfect differentiation of thesignal output suitable for use in generating the measure of hardswitching amplitude.
 9. A circuit according to claim 1, the circuitadapted for incorporation in at least one of: switch mode powersupplies, motor controllers, battery chargers, ionizing apparatus, hightension bias generators.
 10. A method of generating a measure of hardswitching amplitude in a switch mode power supply circuit, the circuitincluding at least one inductive component coupled to an associatedswitch for cyclically connecting the inductive component to a source ofpower, the circuit including a signal output representative of a voltageat a junction of the at least one inductive component to the associatedswitch, the method including the steps of: (a) providing the circuitwith a hard switching amplitude detector for deriving the measure ofhard switching amplitude occurring in operation in the associatedswitch, the detector including a signal processing path for receivingthe signal output and generating the measure of hard switching amplitudetherefrom; (b) imperfectly differentiating the signal output using asignal differentiator circuit included in the signal path for generatinga corresponding imperfectly differentiated signal; and (c) integratingthe imperfectly differentiated signal in a temporally-gated manner in asignal integration circuit included in the signal path for generatingthe measure of hard switching.
 11. A switch mode power supply circuitcomprising: a transformer that includes a primary winding electricallyisolated from a secondary winding; a primary switch for cyclicallyconnecting the primary winding to a power source; a signal outputrepresentative of a primary voltage at a junction of the primary windingto the primary switch; and a hard switching amplitude detector connectedat a junction of the secondary winding to a secondary switch, the hardswitching amplitude detector including a signal processing path forreceiving the signal output and for generating a measure of hardswitching amplitude occurring in operation of the primary switch, thesignal path including a signal differentiator circuit for imperfectlydifferentiating the signal output to generate a correspondingimperfectly differentiated signal, a signal integrator circuit forintegrating the imperfectly differentiated signal in a temporally-gatedmanner for generating the measure of hard switching, and a control unitto provide gating signals to the signal differentiator circuit and thesignal integrator circuit.
 12. The circuit according to claim 11,wherein the control unit is provided with an input signal indicative ofa time interval in which hard switching is expected.
 13. The circuitaccording to claim 11, wherein the signal integrator circuit integratesthe imperfectly differentiated signal for a period initiated upondetection of a switching peak derived from decay in the primary voltagedue to a parasitic capacitance in the primary switch.